1. Field of the Invention
The present invention relates to a semiconductor memory device and method of operating the device.
2. Description of the Related Art
A dynamic random access memory (DRAM) is widely used because of its high density and relative high speed. Since a memory cell typically consists of one transistor and one capacitor, a large number of memory cells can be integrated in DRAM. The memory cell of the DRAM is typically smaller than memory cells of other memory devices, such as a static random access memory (SDRAM), for example.
In a DRAM cell, however, charges stored in each memory cell are reduced after a given time due to leakage current. Therefore, the DRAM cells must be periodically accessed, so that data stored in the capacitors may be refreshed.
The SRAM does not require refreshing, since it includes circuits such as flip-flop circuits that can retain data. The SRAM can therefore achieve high-speed operation, as the flip-flops do not need to be refreshed. However, the flip-flops occupy substantial space per cell, and memory capacity of SRAM is smaller than the memory capacity of DRAM.
DRAM uses two refresh methods: an auto-refresh operation and a self-refresh operation. In the auto-refresh operation, a predetermined timing is allocated during a normal operation of the DRAM and the refresh operation is automatically performed during the allocated timing. A self-refresh operation is performed when the DRAM is in a stand-by mode. The auto-refresh operation and the self-refresh operation are well known in the art, thus a detailed description is omitted.
A pseudo static random access memory (PSRAM) has characteristics of both DRAM and SRAM. PSRAM has an SRAM interface and an array structure configured with DRAM cells. Unlike SRAM, PSRAM needs a refresh operation, since its array structure is configured with DRAM cells. In order to reduce power consumption, a self-refresh operation (as described above) is automatically performed when the PSRAM operates in the stand-by mode. However, there is a potential for loss of data stored in memory cells when the PSRAM is controlling the self-refresh operation while in the stand-by mode.